1. Field of the Invention
The present invention relates to communication transceiver clock and data recovery (CDR) circuits, and, in particular, to improved margin in a data eye in CDR circuitry.
2. Description of the Related Art
In many data communication applications, Serializer and De-serializer (SerDes) devices facilitate the transmission between two points of parallel data across a serial link. Data at one point is converted from parallel data to serial data and transmitted through a communications channel to the second point where it received and converted from serial data to parallel data.
At high data rates, frequency-dependent signal loss from the communications channel (e.g., the signal path between the two end points of a serial link) as well as signal dispersion and distortion can occur. As such, the communications channel, whether wired, optical, or wireless, acts as a filter and might be modeled in the frequency domain with a transfer function. Correction for frequency dependent losses of the communications channel, and other forms of signal degradation, often requires signal equalization at a receiver of the signal. Equalization through use of one or more equalizers compensates for the signal degradation to improve communication quality. Equalization may also be employed at the transmit side to pre-condition the signal. Equalization, a form of filtering, generally requires some estimate of the transfer function of the channel to set its filter parameters. However, in many cases, the specific frequency-dependent signal degradation characteristics of a communications channel are unknown, and often vary with time. In such cases, an equalizer with adaptive setting of parameters providing sufficient adjustable range might be employed to mitigate the signal degradation of the signal transmitted through the communications channel. An automatic adaptation process is often employed to adjust the equalizer's response. Equalization might be through a front end equalizer, a feedback equalizer, or some combination of both.
FIG. 1 shows a data eye diagram 100 overlaid with exemplary data sampler (DS) 102. Data eye diagram 100 illustrates super-positions of many data eyes of signal transitions expressed in amplitude versus time (in unit interval, or “UI”, corresponding to a symbol period). The data eye is created as signals transition from low to low, low to high, high to low and high to high, which transition might also be termed a crossing point. A clock and data recovery (CDR) circuit detects timing of the input data stream and uses such detected timing to set correct frequency and phase of a local clock from which the sampling clock for DS 102 is derived. As employed herein, “placing” a sampler (latch) in a data stream requires setting a voltage threshold and clocking phase of the sampler to detect a predetermined point in the data eye. Clocking the data sampler with a clock signal with known frequency and phase derived with respect to the detected symbol timing of data allows for clock recovery of symbols within the data stream generating the eye.
CDR circuits form a critical part of the receiver in a SerDes device. The objective of the CDR circuit is to track the phase of a sampling clock based on some criterion, such as minimized mean-squared-error (MMSE). To track the phase of a sampling clock based on a given criterion, the CDR circuit generates (timing) error samples with respect to the data sampling clock, and adaptively sets the local clock phase used to derive the data sampling clock so as to minimize the timing error with respect to the chosen criterion. The CDR circuit desirably operates so as to achieve very low target bit-error-ratio (BER) (usually, on the order of 1e-12 or 1e-15). The CDR circuits commonly employed might be broadly classified into two categories: baud-rate CDR circuits and bang-bang CDR circuits, with each class having associated advantages and disadvantages.
In bang-bang or Alexander type CDR circuits, the received signal is sampled twice every symbol period, which is the “unit interval” (UI) above. Ideally, one sample is at the crossing boundary and another at the center of the eye. Two consecutive data samples, (d[k−1] and d[k]), and one crossing sample between them, (p[k]), are used to decide whether the current sampling phase is lagging or leading the ideal sampling point and, if either lagging or leading, is corrected accordingly. In a bang-bang CDR circuit, the eye looks symmetric about the sampling point, which is generally desirable for enhanced sinusoidal jitter tolerance. However, oversampling the received signal adds cost and complexity to, for example, a given implementation of a SerDes receiver.
In a baud-rate CDR circuit, the received signal is sampled at the baud rate, i.e., once every UI, so oversampling is not required. The sampling phase might be selected based on different criteria. For example, in a MMSE baud-rate CDR, the sampling phase which yields MMSE is chosen. The phase detector equation implemented in a baud-rate CDR relies on the error samples and the decisions. For example, in a Mueller-Muller CDR, the phase update equation to update phase τk to phase τk+1 is given in equation (1):τk+1=τk−μ(ek−1dk−ekdk−1)  (1)where dk and ek are the decisions and the error samples, respectively, where ek=(y(τk)−γdk), y(t) is the input signal (usually the output of an equalizer) to a slicer (employed to generate a decision for the input sample) and γ is the reference voltage, which might also be adapted. The error samples are obtained at the same phase, τk, where the data is sampled. Consequently, the error samples are employed as timing error samples by a timing adaptation loop, and the error samples are employed as data error samples by an equalizer adaptation loop if the receiver includes adaptive equalization.
Therefore, if the receiver incorporates a decision feedback equalizer (DFE), the error samples also drive the adaptation of the DFE taps. Returning, to FIG. 1, the data latch DS 102, is shown with positive (top eye edge) and negative (bottom eye edge) error latches 104 and 105 placed above and below at sampling phase instant τk. In a Mueller-Muller baud-rate CDR (MM-CDR) circuit, the sampling phase is chosen such that the 1st pre-cursor and the 1st post-cursor values of the equalized pulse about the sampling point are approximately equal. Thus, the sampling point chosen may not be the center of the equalized eye if the equalized pulse is not symmetrical in terms of 1st pre-cursor and 1st post-cursor values.
Ideally, without noise, jitter, and other loss and dispersion effects, the data eye will exhibit a relatively ideal shape with large amplitude and phase margin, illustrated by area 110. In practice, as described previously, the shape of the data eye changes, illustrated by the traces in FIG. 1, providing a reduced area 111. The shape of the data eye changes with noise, jitter, other loss and dispersion effects, and temperature and voltage variations. The shape of the data eye also changes due to equalization applied to input signal of the receiver. In some systems, equalization is also applied by a transmitter's equalizer, further altering the shape of the eye from the ideal. After equalization, the inner eye of the transceiver is open, with some margin for supporting channels. If a simple, analog front-end equalizer (AFE) is employed, the data eye operating margin improves. However, better performance might be achieved through use of a DFE in combination with an AFE. Classical DFE equalization optimizes for ISI and opens up the vertical and horizontal data eye opening.